Workers in data processing are aware that systems having two or more processors and a number of memory units are commonly used (e.g. see U.S. Pat. Nos. 4,920,484, 3,676,860).
Workers are also familiar with the practice of associating one or several host central processors (CPUs) with an array of memory units via intermediate controllers (e.g. see U.S. Pat. Nos. 4,982,324, 4,413,317, 3,889,237, 4,183,084, 3,623,014). And, today, it is not uncommon to operatively associate an array of peripheral storage units with a host computer via an appropriate controller device. FIG. 1 schematically suggests this for a host H and a number of like memory units D, connectible to H via a controller unit C, including suitable interfaces 1F, 1F' (e.g. see ports 1-4, each connected to a respective, like-numbered drive-port).
Similarly, it may often be desirable to so associate two (or more) host computers with a number of such memory units (storage devices)--e.g. as schematically indicated in FIG. 2, with one host HI coupled to an associated controller C1, a second host H2, also coupled to a respective associated controller C2, and memory units D. If units D are dual-ported, as here indicated, they may be connectible to either host/controller array (as indicated by the port numbers).